In single chip integrated circuits, especially those designed using synchronous design techniques, there are many applications where more than one clock is required. Consideration must be given to any control or data signals which pass from any one clock environment to any other clock environment.
Consider a single bit of a data or control signal arriving from a first clock environment, at the input of a clocked storage element or latch of a second clock environment. Depending on the timing of a change in the single bit of the data or control signal (the timing of which is determined by the first clock environment), there are three possibilities as to whether the single bit of the data or control signal will be stored or "captured" in the clocked storage element of the second clock environment. The three cases are:
i) If the data changes well before the significant clock edge of the second timing environment, then the data is captured and transferred to the latch output shortly after the clock edge of the second timing environment; PA1 ii) If the data changes just after the significant clock edge of the second timing environment, then there is no change to the latch output until the next clock edge of the second timing environment; or PA1 iii) If the data changes close to the significant clock edge of the second timing environment, then the data may be captured on that clock edge and transferred to the latch output shortly after the clock edge, or the data may not be captured without any change to the latch output until after the next clock edge of the second timing environment. Furthermore, there is a finite probability that the latch will enter a "meta-stable" condition where the data is not cleanly captured and the output is liable to change an undetermined time after the clock edge of the second timing environment.
If the latch does enter the meta-stable condition described in (iii), then the delay before the output changes could be longer than one clock cycle depending on the clock frequencies and design of the latch. This means that the output of the latch is indeterminate, the output from successive latches in the design could also be indeterminate, and the collective state of the entire chip rapidly becomes indeterminate.
The effects of metastability can never be completely removed, no matter what technology is used, since it is a fundamental principle of decision making. However, with reasonable design techniques, the probability of metastability propagating in an undesirable manner, can be reduced to an acceptable level. Such acceptable levels may range from the probability of one failure in a year to one failure in an entire product range in a century. This is even more important when there is no relationship between the two clocks and they are said to be asynchronous with respect to each other. Even if two clocks are running at nominally the same frequency, if they have been derived from independent sources then, however tight the tolerances on the frequencies are, the clocks are likely to be drifting with respect to each other.
A known technique for passing a single bit of information between clock environments is to use a special latch which is designed to minimize the effects of metastability, commonly known as a synchronizer. If the time period for an acceptable probability of propagated metastability is longer than one clock cycle, then synchronizers are joined in series such that the output of the last synchronizer has an acceptable probability of failure.
There are many techniques for passing control information between clock environments. The choice of technique depends on the ranges of the clock frequencies of the environments. The cost of the control synchronization may be measured in terms of the delay, or latency, in passing the control information and in terms of the number of synchronizers involved. Typically the number of control signals passed across a clock environment boundary is minimized.
In order to minimize the number of signals which have to pass through synchronizers, only a few control signals pass through the synchronizers and the remainder of the control signals are treated as data. A typical control signal passing in the same direction as the data across the clock boundary may indicate that the data is stable, and a typical control signal passing in the opposite direction may indicate the data has been accepted.
If the data being passed across the clock environment boundary is stable when it is being clocked into the receiving clock environment, then it does not suffer from metastability and does not need to pass through synchronizers. However, the data must remain stable and not change from some time before the control signal indicates that the data is stable up until the control signal in the opposite direction, after it has passed through its synchronizer, indicates that the data has been accepted. This means that the data must be stored and remain unchanged for many clock cycles. If the desired data transfer rate is slower than this number of clock cycles, there is no problem. However, as is more usual, there may be new data arriving at every clock cycle.
For every data bus width of data arriving at every clock cycle, it is possible to arrange the data arriving in several successive cycles to be stored and transferred across a significantly wider bus width. For example, if the width of the data bus is 8 bits, namely a byte, then each byte can be stored until there are 8 bytes, then these 8 bytes transferred across the clock boundary using a 64-bit bus for example.
While the first 8 bytes are being held stable for transfer across the clock boundary, further bytes could be arriving. These further bytes have to be stored separately. For given data rates, the ranges of each of the clock frequencies, the delays of the synchronizers, and the overall latency of the control protocol used, it is possible to determine how much storage is necessary to support the maximum sustainable data rate.
If the protocol latency is 8 cycles and the width of the data bus is 8 bits, then the width of the data bus crossing the clock boundary must be 64 bits. This 64 bits must be held in some storage so that it is stable whilst it is crossing the clock boundary. Thus the amount of storage required is: EQU (Protocol Latency).times.(bus width)
Since new data, on the 8 bit bus, may continue to arrive while the 64 bits are being held stable for crossing the clock boundary, this new data must be stored somewhere, and thus the amount of storage required is: EQU 2.times.(Protocol Latency).times.(bus width)
A similar scheme is also required in the second clock environment. One 64 bits worth of buffering to capture the data passed across the boundary, and a second 64 bits of buffering to hold the data from the previous transfer being passed deeper into the second clock environment 8-bits at a time. Thus, the total amount of storage required on both sides of the boundary is modified to: EQU 4.times.(Protocol Latency).times.(bus width)
Furthermore, according to the protocol used, each synchronizer is a 1-bit data storage element, so the number of synchronizers is added to give the total storage required as: EQU 4.times.(protocol Latency).times.(bus width)+synchronizers
There are a number of different schemes for implementing the protocol to guarantee safe transference of data across a clock boundary. However, in each case, there is a determined protocol latency and a large amount of data storage is required.
In one prior art technique, data is stored in flip-flops prior to transmission across the clock boundary. A large number of flip-flops are needed to store the necessary volume of data, and such an arrangement is expensive in terms of the chip space consumed by the flip-flop circuits.